IEEE

WCET Estimation for CNN Inference on FPGA SoC With Multi-DPU Engines

Abstract: The Deep Learning Processor Unit (DPU) released in the official Xilinx Vitis AI toolchain stands as a commercial off-the-shelf solution tailored for accelerating convolutional neural network ...
IEEE

Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs

Abstract: Designs implemented on field-programmable gate arrays (FPGAs) via high-level synthesis (HLS) suffer from off-chip memory latency and bandwidth bottlenecks. FPGAs can access both large but ...
GitHub

A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond

conda install --channel https://sharc-lab.github.io/HLSFactory/dist-conda hlsfactory # or mamba install --channel https://sharc-lab.github.io/HLSFactory/dist-conda ...
GitHub

An FPGA Accelerator for Transformer Inference

We accelerated a BERT layer across two FPGAs, partitioned into four pipeline stages. We conduct three levels of optimization using Vitis HLS and report runtimes. The accelerator implements a ...