EDN

How to manage changing IP in an evolving SoC design

In a previous article, Getting started in structured assembly in complex SoC designs, an unexceptional system-on-chip (SoC) design was shown to contain hundreds of intellectual property (IP) blocks.
EDN

System-on-chip (SoC) design is all about IP management

For most system-on-chip (SoC) designs, the most critical task is not RTL coding or even creating the chip architecture. Today, SoCs are designed primarily by assembling various silicon intellectual ...
Semiconductor Engineering

Unlocking Efficiency: The Power Of IP Blocks In Silicon Chip Design

The fastest, most efficient and cost-effective way to design silicon is by leveraging intellectual property (IP) blocks. This methodology reduces risk, allows a design team to focus on its own ...
Electronic Design

Optimize SoC Design with a Network-on-Chip Strategy

How third-party interconnect IP saves time, lowers risk, and speeds completion. NoC is the predominant SoC interconnect strategy. NoC IP accommodates multiple interconnect protocols and data widths.
Semiconductor Engineering

IP Becoming More Complex, More Costly

Success in the semiconductor intellectual property (IP) market requires more than a good bit of RTL. New advances mandate a complete design, implementation, and verification team, which limits the ...
Electronic Design

Adding Cache to IPs and SoCs

Cache memory significantly reduces time and power consumption for memory access in systems-on-chip. Technologies like AMBA protocols facilitate cache coherence and efficient data management across CPU ...