The future of design is here, and artificial intelligence (AI) is rapidly becoming a powerful ally in the world of signal integrity. AI isn’t just about doing more with less; it’s about doing things ...

As every engineer learns at an early stage, clock edges must be obeyed. In the digital domain, synchronization through global and local clock trees, slew rate and rising/falling times all combine to ...

Signal integrity is a critical design consideration in modern electronic systems, particularly those that depend on high-speed interconnects. As data rates climb and interconnect geometries become ...

At process technologies of 0.13 µm and smaller, achieving timing closure for system-on-a-chip (SoC) designs becomes a slippery goal. Ever-tinier interconnects are packed closer together, yielding ...

To achieve gains in power, performance, area, and cost, 3D-IC architectures are pushing electronics design to new limits. Silicon integration technology and associated devices have undergone an ...

Analyzing high speed datacom interfaces is an important task and ensures signal integrity. One major challenge of this analysis is the connection between the physical interface and the oscilloscope, ...

Improves PCIe design productivity using a smarter and streamlined workflow with simulation-driven virtual compliance test solutions Supports design exploration and report generation that speeds ...

Races, missed next-state values due to long paths, and metastability can result from corrupted clock signals. This post describes the challenges of clock network and clock jitter analysis in more ...

For those of us who have been evangelizing signal integrity (SI) sign-off, something exciting happened in the first part of 2002. According to the second quarter 2002 EDA Consortium report, the market ...